Continuous-Time Adaptive Delay System - Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

We have developed a direction-selective system that has a row of pixels with photodiodes as the front-end. The output of each photodiode is converted to a digital signal, which is then fed to an adaptive-delay block within each pixel. The adaptive block adjusts an internal delay such that the delay matches the phase offset between the rising edges of this digital signal and the corresponding digital signal from the neighboring pixel. The system does this delay matching by using a dynamic current source to adapt the bias voltage that controls the delay. The adaptive-delay block is similar to a digital charge-pump phaselock loop (PLL). It differs from conventional PLL’s however, both in its compact size and its lack of a system clock. It also has a fast pull-in time during the locking of the signal. Since our application does not require low jitter, we have not introduced a phase offset in the comparator as is typically done in PLL’s. The transistors here are operated in subthreshold. A stability analysis of the feedback system leads to simple stability and convergence constraints. Experimental results from circuits fabricated in 2 pm CMOS technology show that the circuit can lock over 5 decades of frequency.